Introduction of Verilog Mode and Emacs (Updated)10/18/2021 Tags: Verilog
The Verliog design has several duplicate informations, such as argument lists, sensitivity lists, and cross-module wire statement. This feature may causes potential errors by manually programing, lack of maintainability, and overall code bloat.
The verilog-mode supports autogen features to eliminate duplicate effort, looking for keyword (/*AUTO*/) in the verilog code and expand them into appropriate text. Though this autogen features can speed coding, does not mean not exist compile or lint errors in your RTL design.
Make sure your operating system with a recent GUN Emacs (my MACOS is installed GNU Emacs 26.1 version) since the old version of Emacs may not support Verilog-mode execution. Please check your Emacs load-path and see the instructions at the top of the .el or .elc file for details.
Emacs is a family of text editors, like vim and notepad++. The emacs fans describe it as “the extensible, customizable, self-documenting and real-time display editor”. It is, along with vi, one of the two main contenders in the traditional editor wars of Unix clture.
- Check Emacs version
- Install on macOS
$ emacs --version GNU Emacs 26.1 Copyright (C) 2018 Free Software Foundation, Inc. GNU Emacs comes with ABSOLUTELY NO WARRANTY. You may redistribute copies of GNU Emacs under the terms of the GNU General Public License. For more information about these matters, see the file named COPYING.
# Upgrade brew open-source software package management system $ brew update # Install emacs $ brew install emacs # Symlink in the App folder $ brew linkapps emacs
Common Emacs Shortcuts
- Save file: ctrl + x -> ctrl + s
- Close file: ctrl + x -> ctrl + z
- Copy: alt + w
- Paste: ctrl + y
The Verilog AUTOS are in use by many of the leading IP providers, including IP processor cores sold by MIPS and ARM.
The describe-function in Emacs load-path
The verilog-mode features have been implemented by Emacs Lisp code loading verilog-auto functions, similar to load-library, but is lower-level and accepts additional arguments.
# The verilog-mode.elc in Emacs load-path: emacs/26.1/lisp/progmodes/verilog-mode.elc $ less verilog-mode.elc ... 3124 Using \[describe-function], see also: 3125 `verilog-auto-arg' for AUTOARG module instantiations 3126 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding 3127 `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport ...
Demo Emacs Verilog-mode
# Clone Verilog_Mode repo $ git clone https://github.com/s311354/Verilog_Mode.git # Enter Verilog_Mode directory and execute emacs $ emacs VerModeDemo.v # Execute verilog-auto function: ctrl + c -> ctrl + a
The verilog-auto-arg (function) replaces the argument declarations at the beginning of the module with ones automatically derived from input and output statements. Recommending for using only name-based when instantiating the resulting module.
The verilog-auto-inst (function) replaces the pin connections to an instantiation or interface declaration with ones automatically derived from the module or interface header of the instantiated item.
If any ports defined before the /*AUTOINST*/ are not included in the list of automatics, you should connect pin by yourseld just like you normally make.
The verilog-auto-input (function), verilog-auto-output (function) and verilog-auto-inout (function) make input statements for any input, any output, and inout signals into an /*AUTOINST*/ that aren’t declared elsewhere inside the module. This is useful for modules which only instantiate other modules.
For another function, verilog-auto-reg-input (function), it makes reg statements instantiation inputs that aren’t already declared just like verilog-auto-input (function).
The verilog-auto-wire (function) makes wire statements for instantiations outputs that aren’t already declared.
The verilog-auto-reg (function) makes reg statements for any output that isn’t already declared, and isn’t a wire output from a block.
The verilog-auto-reset (function) replaces the /*AUTORESET*/ comment with code to initialize all registers set elsewhere in the always block.
The verilog-auto-sense (function) replaces the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short) with one automatically derived from all inputs declared in the always statement.
The verilog-auto-tieoff (function) replaces the /AUTOTIEOFF/ comment with code to wire-tie all unused output signals to deasserted. For another function, it replaces the /AUTOUNUSED/ comment with a comma separated list of all unused input and inout signals.
The verilog-auto-ascii-enum (function) creates a register to contain the ASCII decode of an enumerated signal type. Normally, this function is used to create the finite state machine (FSM), but the default the bitwidth of nextstate and state information should be reviewed and manually modified.
This feature is used to customize the parameter connections to an instantiation or create multiple instantiations based upon a single template.
For an example:
// Regular expression Condition: "_\([a-z0-9]+\)" /* InstModule AUTO_TEMPLATE "_\([a-z0-9]+\)" ( .out (@_constant_pin), ); */ InstModule sub_RAM1 (/*AUTOINST*/); InstModule sub_RAM2 (/*AUTOINST*/);
 Editor war
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